1. Field of the Invention
The present invention relates to a Phased Locked Loop (PLL) circuit, phase shifting method, and Integrated Circuit (IC) chip, and particularly relates to a PLL circuit, phase shifting method, and IC chip configured to improve reception precision without increasing clock frequency.
2. Description of the Related Art
Heretofore, for non-contact IC card communication, a digital Phased Locked Loop (PLL) such as a Costas-Loop has been used in order to extract a sampling clock from a digital signal subjected to Phase Shift Keying (PSK) modulation with Manchester encoding (for example, see Japanese Unexamined Patent Application Publication No. 11-274919)
FIG. 1 is a circuit diagram illustrating an example of a traditional digital PLL. The digital PLL 1 in FIG. 1 is configured with a Costas-Loop, and is made up of a frequency dividing oscillating circuit 11, phase shift circuit 12, Exor circuits 13a and 13b, and Low Pass Filter (LPF) 14a and 14b. 
With the frequency dividing oscillating circuit 11, the clock frequency input from an unshown oscillating circuit divides a 13.56 MHz clock signal f_clk eight ways, thereby generating a signal sin(wt+Φ) serving as a 1696 kHz clock signal and supplying this to the phase shift circuit 12 and Exor circuit 13a. 
The phase shift circuit 12 generates a signal cos(wt+Φ) wherein the phase of the signal sin(wt+Φ) is delayed by Π/2 (90 degrees), and supplies this to the Exor circuit 13b. 
The Exor circuit 13a computes an exclusive OR from the 1696 kbps (kilobit per second) signal DATA serving as a digital signal subjected to Phase Shift Keying (PSK) modulation with Manchester encoding and the signal sin(wt+Φ), generates a signal V1 indicating a value V1 wherein the computed results are inverted (=DATA·sin(wt+Φ), and supplies this to the LPF 14a. 
The Exor circuit 13b computes an exclusive OR from the signal DATA and the signal cos(wt+Φ), generates a signal V2 indicating a value V2 wherein the computed results are inverted (=DATA cos(wt+Φ), and supplies this to the LPF 14b. 
For every 8 clocks of the clock signal f_clk, the LPF 14a adds the value V1 across the period of the 8 clocks, generates a signal ΣV1 indicating an added value ΣV1 (=Σ{DATA sin(wt+Φ), and supplies this to the frequency dividing oscillating circuit 11.
For every 8 clocks of the clock signal f_clk, the LPF 14b adds the value V2 across the period of the 8 clocks, generates a signal ΣV2 indicating an added value ΣV2 (=Σ{DATA·cos(wt+Φ)), and supplies this to the frequency dividing oscillating circuit 11.
The frequency dividing oscillating circuit 11 controls a control angle Φ based on the values ΣV1 and ΣV2 such that the value ΣV2 becomes zero, and causes the phases of the signal DATA and the signal sin(wt+φ) to be synchronized, thereby demodulating the phase of the signal DATA and extracting a sampling clock from the signal DATA.